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Texas Instruments /MSP432P401M /EUSCI_B2 /UCBxIE

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Interpret as UCBxIE

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (UCRXIE0_0)UCRXIE0 0 (UCTXIE0_0)UCTXIE0 0 (UCSTTIE_0)UCSTTIE 0 (UCSTPIE_0)UCSTPIE 0 (UCALIE_0)UCALIE 0 (UCNACKIE_0)UCNACKIE 0 (UCBCNTIE_0)UCBCNTIE 0 (UCCLTOIE_0)UCCLTOIE 0 (UCRXIE1_0)UCRXIE1 0 (UCTXIE1_0)UCTXIE1 0 (UCRXIE2_0)UCRXIE2 0 (UCTXIE2_0)UCTXIE2 0 (UCRXIE3_0)UCRXIE3 0 (UCTXIE3_0)UCTXIE3 0 (UCBIT9IE_0)UCBIT9IE

UCTXIE3=UCTXIE3_0, UCRXIE3=UCRXIE3_0, UCRXIE0=UCRXIE0_0, UCSTTIE=UCSTTIE_0, UCTXIE2=UCTXIE2_0, UCSTPIE=UCSTPIE_0, UCRXIE2=UCRXIE2_0, UCCLTOIE=UCCLTOIE_0, UCNACKIE=UCNACKIE_0, UCTXIE0=UCTXIE0_0, UCTXIE1=UCTXIE1_0, UCBCNTIE=UCBCNTIE_0, UCALIE=UCALIE_0, UCRXIE1=UCRXIE1_0, UCBIT9IE=UCBIT9IE_0

Description

eUSCI_Bx Interrupt Enable Register

Fields

UCRXIE0

Receive interrupt enable 0

0 (UCRXIE0_0): Interrupt disabled

1 (UCRXIE0_1): Interrupt enabled
UCTXIE0

Transmit interrupt enable 0

0 (UCTXIE0_0): Interrupt disabled

1 (UCTXIE0_1): Interrupt enabled
UCSTTIE

START condition interrupt enable

0 (UCSTTIE_0): Interrupt disabled

1 (UCSTTIE_1): Interrupt enabled
UCSTPIE

STOP condition interrupt enable

0 (UCSTPIE_0): Interrupt disabled

1 (UCSTPIE_1): Interrupt enabled
UCALIE

Arbitration lost interrupt enable

0 (UCALIE_0): Interrupt disabled

1 (UCALIE_1): Interrupt enabled
UCNACKIE

Not-acknowledge interrupt enable

0 (UCNACKIE_0): Interrupt disabled

1 (UCNACKIE_1): Interrupt enabled
UCBCNTIE

Byte counter interrupt enable

0 (UCBCNTIE_0): Interrupt disabled

1 (UCBCNTIE_1): Interrupt enabled
UCCLTOIE

Clock low timeout interrupt enable

0 (UCCLTOIE_0): Interrupt disabled

1 (UCCLTOIE_1): Interrupt enabled
UCRXIE1

Receive interrupt enable 1

0 (UCRXIE1_0): Interrupt disabled

1 (UCRXIE1_1): Interrupt enabled
UCTXIE1

Transmit interrupt enable 1

0 (UCTXIE1_0): Interrupt disabled

1 (UCTXIE1_1): Interrupt enabled
UCRXIE2

Receive interrupt enable 2

0 (UCRXIE2_0): Interrupt disabled

1 (UCRXIE2_1): Interrupt enabled
UCTXIE2

Transmit interrupt enable 2

0 (UCTXIE2_0): Interrupt disabled

1 (UCTXIE2_1): Interrupt enabled
UCRXIE3

Receive interrupt enable 3

0 (UCRXIE3_0): Interrupt disabled

1 (UCRXIE3_1): Interrupt enabled
UCTXIE3

Transmit interrupt enable 3

0 (UCTXIE3_0): Interrupt disabled

1 (UCTXIE3_1): Interrupt enabled
UCBIT9IE

Bit position 9 interrupt enable

0 (UCBIT9IE_0): Interrupt disabled

1 (UCBIT9IE_1): Interrupt enabled

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data